• DocumentCode
    2954941
  • Title

    Representing sparse binary matrices as straight-line programs for fast matrix-vector multiplication

  • Author

    Neves, Samuel ; Araujo, Filipe

  • Author_Institution
    Dept. of Inf. Eng., Univ. of Coimbra, Coimbra, Portugal
  • fYear
    2012
  • fDate
    2-6 July 2012
  • Firstpage
    520
  • Lastpage
    526
  • Abstract
    Sparse matrix-vector multiplication dominates the performance of many scientific and industrial problems. For example, iterative methods for solving linear systems rely on the performance of this critical operation. The particular case of binary matrices shows up in many important areas of computing, such as graph theory and cryptography. Unfortunately, irregular memory access patterns cause poor memory throughput, slowing down this operation. To maximize memory throughput, we transform the matrix into a straight-line program that takes full advantage of the instruction cache. The regular loopless pattern of the program minimizes cache misses, thus decreasing the latency for most instructions. We focus on the widely used x86_64 architecture and on binary matrices, to explore several possible tradeoffs regarding memory access policies and code size. When compared to a Compressed Row Storage (CRS) implementation, we obtain significant speedups of up to 4x.
  • Keywords
    cache storage; iterative methods; linear systems; matrix multiplication; memory architecture; multiprocessing systems; sparse matrices; vectors; CRS implementation; cache misses; code size; compressed row storage implementation; cryptography; fast matrix-vector multiplication; graph theory; instruction cache; irregular memory access patterns; iterative methods; linear systems; memory access policy; poor memory throughput; regular loopless pattern; sparse binary matrices; sparse matrix-vector multiplication; straight-line programs; x86_64 architecture; Assembly; Bridges; Matrix converters; Prefetching; Registers; Sparse matrices; Vectors; Instruction; Large Scale Scientific Computing; Multi-Core Architectures and Support; Thread and Memory-Level Parallelism;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing and Simulation (HPCS), 2012 International Conference on
  • Conference_Location
    Madrid
  • Print_ISBN
    978-1-4673-2359-8
  • Type

    conf

  • DOI
    10.1109/HPCSim.2012.6266967
  • Filename
    6266967