Title :
A new method to implement a constant operand multiplier
Author :
Kharrat, M.W. ; Ben Ayed, M. Ali ; Loulou, M. ; Masmoudi, N. ; Kamoun, L.
Author_Institution :
Lab. d´´Electronique et des Technol. de l´´Information, Ecole Nationale d´´Ingenieurs de Sfax, Tunisia
Abstract :
In this paper we present a new method to implement constant operand multiplier. The structure is optimized in point of view of surface occupation and time execution. The principle of the new method based on a compression of four partial products into one row. The method proofs its availability for both signed and unsigned multiplication. Simulation results using FPGA implementation technology show an improvement of proposed algorithm performances compared to DADDA multiplier.
Keywords :
field programmable gate arrays; multiplying circuits; DADDA multiplier; FPGA implementation technology; constant operand multiplier; Availability; Design methodology; Design optimization; Field programmable gate arrays; Logic gates; Pulse inverters; Tree data structures;
Conference_Titel :
Microelectronics, The 14th International Conference on 2002 - ICM
Print_ISBN :
0-7803-7573-4
DOI :
10.1109/ICM-02.2002.1161497
