ASIC design margin methodology

On-chip variation (OCV) analysis is one of the design issues faced by STA owners in advance technology node. In the past, typical OCV analysis assumed the worst process variation at transistor channel length as part of process corner definition during timing signoff. However, with the increase of intra-die variations due to the continually shrinking fabrication technology node, traditional process corner definition with timing uncertainty alone is insufficient. A large timing uncertainty will introduce excessive pessimism into the timing budget, as well as unnecessary leakage power, which is undesirable in battery application devices. The intention of this paper is to provide a comparison overview of ASIC design margin methodology for intra-die variations during timing signoff. Hopefully, these findings will benefit the ASIC STA planner in reducing the timing margin, as well as leakage power, through reduction in timing margin pessimism.