Hardware implementations of the data encryption standard

Implementation of cryptographic algorithms on programmable devices FPGAs (Field Programmable Gate Array) run much faster than on software while preserving physical security of hardware solutions. At the same time, these devices allow potentially the same flexibility as software solutions. In fact, they can be reprogrammed on line in order to modify the same algorithm or to implement other cryptographic algorithms. We designed and implemented various architectures of cryptographic algorithm DES (Data Encryption Standard) in Electronic CodeBook Mode (ECB) using hardware description language VHDL (Very High Speed Integrated Circuits Hardware Description Language). We have used pipelining technique and we have analyzed effectiveness of these implementations on FPGAs. The most interesting result is that we could achieve data rate of up to 1 Gbits/s using a standard Altera FPGA (speed-grade = -4). This result is faster than software implementations while we are still maintaining flexibility. However, it still less than hardware solutions based on full custom VLSI (Very Large Scale Integration) integrated circuits.