A 1.5V multigigahertz CMOS tunable image reject notch filter

Author

Baki, Rola A. ; El-Gamal, N.

Author_Institution

Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada

fYear

2002

fDate

11-13 Dec. 2002

Firstpage

144

Lastpage

147

Abstract

This paper presents a new RF notch filter topology for image rejection in heterodyne receivers. The circuit is combined with a cascode low noise amplifier (LNA) and an output buffer for testing purposes. It is implemented with standard CMOS 0.18μm technology. The notch filter is tunable from 10.5 to 11.1GHz. Up to 10dB controllable gain is obtained from the LNA in the pass band at 6.5GHz. A -50dB image rejection is realized by using on chip inductor Q-factor enhancement techniques. At the maximum in band gain of 12dB and -50dB image rejection, the circuit consumes 22mW of power with a noise figure of 2.4dB, a -12.5dB IIP3, from a 1.5V power supply.

Keywords

CMOS analogue integrated circuits; circuit optimisation; heterodyne detection; integrated circuit layout; notch filters; 0.18 micron; 1.5 V; 10 dB; 10.5 to 11.1 GHz; 12 dB; 2.4 dB; 22 mW; 6.5 GHz; CMOS; LNA; RF filter topology; complementary metal oxide semiconductor; heterodyne receiver; image rejection; low noise amplifier; output buffer; tunable notch filter; Band pass filters; CMOS technology; Circuit noise; Circuit testing; Circuit topology; Inductors; Low-noise amplifiers; Radio frequency; Radiofrequency amplifiers; Tunable circuits and devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, The 14th International Conference on 2002 - ICM

Print_ISBN

0-7803-7573-4

Type

conf

DOI

10.1109/ICM-02.2002.1161516

Filename

1161516