Title :
Design for testability, placement and routing of a new oversampled Σ-Δ modulator
Author :
Bo, Ye ; Lan, Huang ; Jun-yan, Ren ; Zeng-Yu, Zheng
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Abstract :
A new top-down design method is proposed in this paper including Verilog hardware description, synthesis, design for testability, library preparation, automatic placement and routing with some artificial interference using a new oversampled Σ-Δ modulator as an example. A theorem is also introduced for DFT consideration
Keywords :
circuit layout CAD; design for testability; integrated circuit layout; network routing; sigma-delta modulation; ADC; DFT; Verilog hardware description; artificial interference; automatic placement; design for testability; library preparation; oversampled Σ-Δ modulator; routing; top-down design method; Application specific integrated circuits; Circuit faults; Circuit testing; Clocks; Delta modulation; Design for testability; Design methodology; Hardware design languages; Routing; Very large scale integration;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562804
