Low power, low voltage, 10bit-50MSPS pipeline ADC dedicated for front-end ultrasonic receivers

Author

El-Sankary, K. ; Kassem, A. ; Chebli, R. ; Sawan, M.

Author_Institution

Dept. of Electr. Eng., Ecole Polytechnique de Montreal, Que., Canada

fYear

2002

fDate

11-13 Dec. 2002

Firstpage

219

Lastpage

222

Abstract

This paper concerns the design and the implementation of a low power, low voltage 10bit-50MS/s pipeline analog to digital converter (ADC) dedicated to ultrasonic receivers. The ADC is used in the front-end stage to convert the signals coming from the time gain compensator (TGC) of the handheld ultrasonic apparatus. The proposed architecture is based on 1.5 bits per stage pipeline structure followed by a digital offset compensation to relax the constraints on the analog circuitry. The converter is implemented in digital CMOS 0.18 μm technology, the circuit occupies an active area of 1.2 mm², the input differential voltage dynamic range is chosen to be 1.6 Vpp and the power consumption is found to be 31 mW from 1.8 V supply.

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; pipeline processing; receivers; ultrasonic devices; 0.18E-6 m; 1.8 V; 31E-3 W; ADC; CMOS technology; TGC; analog circuitry; analog to digital converter; digital offset compensation; front-end stage; handheld ultrasonic apparatus; pipeline structure; time gain compensator; ultrasonic receivers; Analog-digital conversion; CMOS digital integrated circuits; CMOS technology; Delay; Dynamic range; Energy consumption; Laboratories; Low voltage; Pipelines; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, The 14th International Conference on 2002 - ICM

Print_ISBN

0-7803-7573-4

Type

conf

DOI

10.1109/ICM-02.2002.1161534

Filename

1161534