• DocumentCode
    2955704
  • Title

    New ATPG algorithm for iDDT-based testing

  • Author

    Chehab, Ali ; Makki, Rafic ; Maddali, Raghudar

  • Author_Institution
    Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Lebanon
  • fYear
    2002
  • fDate
    11-13 Dec. 2002
  • Firstpage
    224
  • Lastpage
    227
  • Abstract
    In this paper we present a new ATPG algorithm and its software implementation for the automatic generation of input vector pairs specific for iDDT-based test methods. The algorithm attempts to switch every net in the circuit, to minimize the total number of required test vectors and to minimize the switching activity in he circuit. We present the results of the application of the ATPG to the ISCAS´85 benchmark circuits and show the switching profiles of the benchmark circuits.
  • Keywords
    algorithm theory; automatic test pattern generation; benchmark testing; integrated circuit testing; ATPG algorithm; IDDT-based testing; automatic generation; benchmark circuits; circuit switching activity; input vector pairs; software implementation; switching profiles; test vectors; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Costs; Integrated circuit interconnections; Manufacturing; Semiconductor device testing; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, The 14th International Conference on 2002 - ICM
  • Print_ISBN
    0-7803-7573-4
  • Type

    conf

  • DOI
    10.1109/ICM-02.2002.1161535
  • Filename
    1161535
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2955704