A high-level data path allocation algorithm based on BIST testability metrics

Author

Tianruo Yang, Laurence ; Muzio, Jon

Author_Institution

Dept. of Comput. Sci., St. Francis Xavier Univ., Antigonish, NS, Canada

fYear

2002

fDate

11-13 Dec. 2002

Firstpage

232

Lastpage

236

Abstract

In this paper, we describe a BIST testability metric-based high-level data path allocation algorithm to facilitate Built-In Self-Test designs. We will describe register transfer level data path testability metrics to evaluate various BIST configurations and make improvement decision during the data path allocation. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.

Keywords

algorithm theory; built-in self test; design for testability; high level synthesis; integrated circuit design; integrated circuit testing; BIST configurations; BIST testability metrics; Built-In Self-Test designs; data path allocation; data path testability metrics; improvement decision; register transfer level; Automatic testing; Built-in self-test; Circuit testing; Computer science; Costs; Digital circuits; Hardware; High level synthesis; Registers; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, The 14th International Conference on 2002 - ICM

Print_ISBN

0-7803-7573-4

Type

conf

DOI

10.1109/ICM-02.2002.1161537

Filename

1161537

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2955726