Fast and robust CMOS double pipeline using new TSPC multiplexer and demultiplexer

New multiplexer and demultiplexer are proposed for a fast and robust CMOS double pipeline, based on new TSPC latches. The speed bottlenecks of the CMOS double pipeline are consequently removed and the critical delays are reduced by a factor of two approximately. The input latching window is widened significantly by reducing the input hold times. The robustness of the double pipeline is thus improved. A single clock is used throughout the whole structure. Simulation results are presented, showing the increased speed and the reduced hold times