DocumentCode :
2956249
Title :
Improving the Detectability of Resistive Open Faults in Scan Cells
Author :
Yang, Fan ; Chakravarty, Sreejit ; Devta-Prasanna, Narendra ; Reddy, Sudhakar M. ; Pomeranz, Irith
Author_Institution :
ECE Dept., Univ. of Iowa, Iowa City, IA, USA
fYear :
2009
fDate :
7-9 Oct. 2009
Firstpage :
383
Lastpage :
391
Abstract :
Recent studies have shown that new tests are required for the detection of a large percentage of scan cell internal open faults which are not detected by the existing tests. However, the additional coverage due to the new tests drops significantly when opens with moderate resistances are considered. In this paper we propose to augment earlier test methods to detect internal scan chain opens with a wider range of resistances. The newly proposed method includes application of tests at higher temperatures and modifications to an earlier proposed flush test. We also present an analysis to explain the additional coverage obtained by the proposed test methods.
Keywords :
automatic test pattern generation; fault diagnosis; logic testing; automatic test pattern generation; fault detection; flush test; internal scan chain; resistive open faults; scan cells; stuck-open faults; Automatic test pattern generation; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit interconnections; System testing; Temperature; USA Councils; Very large scale integration; faults in scan cells; high temperature testing; leakage current effects; resistive open faults;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
Conference_Location :
Chicago, IL
ISSN :
1550-5774
Print_ISBN :
978-0-7695-3839-6
Type :
conf
DOI :
10.1109/DFT.2009.30
Filename :
5372235
Link To Document :
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