A 2.5 V, 2.0 GByte/s packet-based SDRAM with a 1.0 Gbps/pin interface

Author

Kim, C. ; Kyung, K.-H. ; Jeong, W.-P. ; Kim, J.-S. ; Moon, B.-S. ; Yim, S.-M. ; Chai, J.-W. ; Choi, J.-H. ; Lee, C.-K. ; Han, K.-H. ; Park, C.-J. ; Choi, H. ; Cho, S.-I.

Author_Institution

Memory Div., Samsung Electron. Co. Ltd., Kyungi, South Korea

fYear

1998

fDate

11-13 June 1998

Firstpage

104

Lastpage

105

Abstract

A 2.5 V, 72 Mbit packet protocol based SDRAM (PSDRAM) achieving a peak bandwidth of 2.0 GByte/s has been developed with a 0.23 /spl mu/m twin-well, 4-poly, 2-metal CMOS process. An internal Vcc of 2.0 V and V/sub term/ of 1.8 V with 0.8 V signal swing are used in the array to reduce the sensing power and I/O switching power, respectively. The total maximum chip power consumption of 1.80 W, including the average I/O switching power of 0.25 W, has been achieved when internal 16 banks are interleavingly operated with 20 ns interval commands at 2.0 GByte/s, Vcc=2.7 V, and T=25/spl deg/C.

Keywords

CMOS memory circuits; DRAM chips; VLSI; 0.23 micron; 1 Gbit/s; 1.8 W; 2 GByte/s; 2.5 V; 72 Mbit; I/O switching power reduction; chip power consumption; packet protocol; packet-based SDRAM; sensing power reduction; synchronous DRAM; twin-well CMOS process; Access protocols; Bandwidth; Circuit noise; Clocks; Decoding; Delay; Energy consumption; Prefetching; Random access memory; SDRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688016

Filename

688016