Title :
Design and research of 8-bit Multiplier designed by maximum delay-difference stream-line processing
Author :
Youming, Feng ; Weimin, Li ; Da, Wan
Author_Institution :
CASET, Beijing, China
Abstract :
An 8-bit Multiplier about the critical technology in parallel manipulating and high-performance processing was designed and manufactured in our laboratory. The suitable logic units and conversion were designed to decrease the disadvantageous effects of CMOS circuits effectively and raise circuit speed. Redundant inverter logic was used to adjust the length of the logic chains. The circuit was disunited into parts according to wafer structure and the characteristic of circuits. The logic simulation and post layout simulation were adapted to adjust the delay of logic chains
Keywords :
CMOS logic circuits; multiplying circuits; parallel processing; 8 bit; CMOS circuit; conversion; design; logic chain delay; logic simulation; logic unit; maximum delay-difference stream-line processing; multiplier; parallel processing; post layout simulation; redundant inverter logic; Adders; CMOS logic circuits; Circuit simulation; Delay effects; Delay lines; Frequency; Logic circuits; Logic design; Process design; Pulse inverters;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562810
