Title :
A 2 K-gate high performance merged complementary BiCMOS gate array
Author :
Jian-Ming, Wang ; Tai, Gu ; Yun, Huang ; Wei, Tang
Author_Institution :
Central Res. Inst. of China, Huajing Electron. Group Corp., Jiangsu, China
Abstract :
Using high performance merged complementary BiCMOS circuit structure, a 2 K-gate BiCMOS gate array master slice and its unit cell library have been designed and created by 2 μm rules. On this master slice, a double 64 bits high speed shift register has also been customized. An internal gate delay of the gate array is 0.65 ns (typical). The operating frequency of the custom IC is more than 100 MHz
Keywords :
BiCMOS digital integrated circuits; BiCMOS logic circuits; application specific integrated circuits; integrated circuit design; integrated circuit technology; logic arrays; shift registers; 0.65 ns; 100 MHz; 2 micron; ASIC design; custom IC; gate array master slice; high speed shift register; merged complementary BiCMOS gate array; unit cell library; BiCMOS integrated circuits; CMOS process; CMOS technology; Frequency; Ion implantation; Logic arrays; Logic design; MOS devices; Plasma temperature; Shift registers;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562814
