Clock period optimization in a multiphase edge-clocked circuit constrained to a maximum number of phases

Author

Fernández, Felipe ; Sánchez, Angel

Author_Institution

Dept. Tecnologia Fotonica, Univ. Politecnica de Madrid, Spain

fYear

1997

fDate

1-4 Sep 1997

Firstpage

184

Lastpage

189

Abstract

Presents a timing graph technique for the optimization of multiple-phase edge-clocked circuits. By using this method, the timing of these synchronous systems can be analyzed and designed accurately, taking into account the corresponding temporal parameters involved. An optimization algorithm, which includes the effects of the setup and hold time and the propagation delays of the registers, is introduced. The optimal phase distribution is obtained by means of an integer linear program. An iterative procedure for constraining the maximum number of phases is also proposed

Keywords

circuit analysis computing; circuit optimisation; clocks; delays; flip-flops; integer programming; iterative methods; linear programming; logic circuits; signal flow graphs; timing; timing circuits; circuit graph model; clock period optimization algorithm; hold time; integer linear programming; iterative procedure; maximum phase number constraint; multiphase edge-clocked circuit; optimal phase distribution; register propagation delays; setup time; synchronous systems; temporal parameters; timing graph technique; Circuits; Clocks; Constraint optimization; Delay; Flow graphs; Integer linear programming; Power system modeling; Registers; Signal processing algorithms; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

EUROMICRO 97. 'New Frontiers of Information Technology'. Short Contributions., Proceedings of the 23rd Euromicro Conference

Conference_Location

Budapest

Print_ISBN

0-8186-8215-9

Type

conf

DOI

10.1109/EMSCNT.1997.658460

Filename

658460