Title :
Shift register diagnostics: an architectural solution
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
This paper presents a shift register connection scheme that provides a consistent method to diagnose a defective shift register within a shift register latch boundary. The approach is practical, since it requires only one extra I/O pin and a minimum amount of additional chip area
Keywords :
fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; shift registers; LSSD circuits; architectural solution; defective shift register; level sensitive scan design; shift register connection scheme; shift register diagnostics; shift register latch boundary; Circuit faults; Circuit testing; Clocks; Integrated circuit interconnections; Latches; Logic circuits; Logic devices; Logic testing; Shift registers; Strontium;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562815
