Accurate on-chip interconnect evaluation: a time domain technique

This paper describes an on-chip sampling and measurement technique for accurate (<15 ps.) evaluation of interconnect delays and coupled noise. We have used this nonintrusive time-domain technique to extract, for the first time, in-situ driver/receiver waveforms, propagation delays and coupled noise in over 100 interconnect structures. The effects studied include: multiple AC returns through active devices, gridded planes on adjacent layers, via impedances, and variable driver impedances. The results provide a comprehensive evaluation of interconnect delays and noise in a 1.8 V, 0.25 /spl mu/m process.