Title :
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points
Author :
Yang, Joon-Sung ; Nadeau-Dostie, Benoit ; Touba, Nur A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
Abstract :
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving the control points. This paper investigates methods to further reduce the area overhead by replacing dedicated flip-flops which could not be replaced in [Yang 09]. A new algorithm (alternative selection algorithm) is proposed to find candidate flip-flops out of the fan-in cone of a test point. Experimental results indicate that most of the not-replaced flip-flops in [Yang 09] can be replaced and hence even more significant area reduction can be achieved with minimizing the loss of testability.
Keywords :
VLSI; built-in self test; flip-flops; BIST; VLSI; alternative selection algorithm; built-in self-test; control test points; fan-in cone; functional flip-flops; test point area; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Controllability; Electrical fault detection; Fault detection; Flip-flops; Logic testing; Test pattern generators; Alternative Selection Algorithm; BIST; Test Point Insertion; Use of Functional Flip-Flops to Drive Control Points;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
978-0-7695-3839-6
DOI :
10.1109/DFT.2009.33
