• DocumentCode
    2957008
  • Title

    Adder based residue to binary converters for a new balanced 4-moduli set

  • Author

    Cao, Bin ; Chang, Chip-Hong ; Srikanthan, Thambipillai

  • Author_Institution
    Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore
  • Volume
    2
  • fYear
    2003
  • fDate
    18-20 Sept. 2003
  • Firstpage
    820
  • Abstract
    In this paper, an efficient residue to binary conversion algorithm is derived for a new four-moduli set {2n-1, 2n, 2n+1, 2n-1-1} with large dynamic range and well-balanced moduli. Our algorithm exploits the special periodicity properties of the proposed moduli set to obtain hardware efficacy. By using the most efficient residue to binary conversion of the three-moduli set {2n-1, 2n, 2n+1}, the proposed algorithm can be reduced to a simpler two moduli set RNS where fast mixed-radix conversion can be used to obtain the weighted binary number. Four different adder-based architectures are proposed, all are pipelinable to achieve very high throughput rate, and all are more efficient than the residue to binary converters for other four-moduli sets in terms of area and delay.
  • Keywords
    adders; pipeline arithmetic; residue number systems; signal processing; adder-based architecture; binary conversion algorithm; four-moduli set; mixed-radix conversion; weighted binary number; Cathode ray tubes; Delay; Digital signal processing; Digital systems; Dynamic range; Embedded system; Fault tolerant systems; Hardware; Table lookup; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the 3rd International Symposium on
  • Print_ISBN
    953-184-061-X
  • Type

    conf

  • DOI
    10.1109/ISPA.2003.1296391
  • Filename
    1296391