DocumentCode
2957017
Title
Testing techniques for embedded memories in ASIC
Author
Jin, London
Author_Institution
Adaptec Inc., Milpitas, CA, USA
fYear
1996
fDate
21-24 Oct 1996
Firstpage
376
Lastpage
379
Abstract
This paper provides a survey of four practical testing techniques for embedded memories in ASIC in industry. The pros and cons of these techniques are studied in terms of area, timing, power, pin count, automation, test speed, test quality and chip testing
Keywords
application specific integrated circuits; integrated circuit testing; timing; ASIC; area; automation; chip testing; embedded memories; pin count; power; test quality; test speed; testing techniques; timing; Application specific integrated circuits; Asynchronous transfer mode; Automatic testing; Design automation; Internet; Libraries; Multimedia communication; Read-write memory; Registers; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562831
Filename
562831
Link To Document