Title :
P+P: parallel pattern and parallel fault simulator for synchronous sequential circuit
Author :
Houpeng, Chen ; Yuan, Lu ; Zhenghui, Lin
Author_Institution :
VLSI Res. Inst., Shanghai Jiaotong Univ., China
Abstract :
This paper describes P+P, a fast fault simulator for synchronous sequential circuits. P+P uses parallel patterns in good machine simulation (GMS) and parallel faults in faulty machine simulation (FMS). In addition, P+P features several new techniques, such as global circuit levelization, cone operation, global fault grouping, levelized events and improved ID etc., in order to increase performance. The algorithm is realized on SUN SPARC-2 with random patterns. P+P runs on most of the ISCAS benchmark circuits. These experiments show that P+P is much faster than primary P+P algorithm
Keywords :
VLSI; circuit analysis computing; fault diagnosis; flip-flops; integrated circuit testing; logic testing; sequential circuits; ISCAS benchmark circuits; SUN SPARC-2; cone operation; faulty machine simulation; global circuit levelization; global fault grouping; good machine simulation; levelized events; parallel fault simulator; parallel pattern; random patterns; synchronous sequential circuit; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Flip-flops; Logic testing; Sequential analysis; Sequential circuits; Sun; Very large scale integration;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562832
