A high density integrated test matrix of MOS transistors for matching study

Author

Portmann, Lionel ; Lallement, Christophe ; Krummenacher, Franqois

Author_Institution

Electron. Lab., Fed. Inst. of Technol., Lausanne, Switzerland

fYear

1998

fDate

23-26 Mar 1998

Firstpage

19

Lastpage

24

Abstract

This paper describes a test structure for the characterization of MOS transistor matching. It integrates (on 1.5 mm square) a matrix of 480 transistors to be tested, together with the analog switches and shift registers necessary for individual access to these transistors. This circuit has been integrated on an experimental fully depleted silicon on insulator (SOI) process as well as on a standard bulk process. Results for the SOI matching properties are discussed

Keywords

CMOS integrated circuits; MOSFET; integrated circuit testing; integrated circuit yield; shift registers; silicon-on-insulator; 1.5 mm; CMOS process matching; MOS transistor matching; MOS transistors; SOI matching properties; analog switches; circuit integration; fully depleted SOI process; fully depleted silicon on insulator process; high density integrated test matrix; shift registers; standard bulk process; test structure; Circuit testing; Force measurement; Integrated circuit technology; MOS devices; MOSFETs; Shift registers; Substrates; Switches; Transistors; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on

Conference_Location

Kanazawa

Print_ISBN

0-7803-4348-4

Type

conf

DOI

10.1109/ICMTS.1998.688028

Filename

688028