Title :
System level test generation and fault simulation for VLSI circuits
Author :
Ma, Yuhai ; Sun, Yihe ; Chen, Hongyi
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
This paper presents a new concept in VLSI test domain: System Level Test Generation and Fault Simulation. In the paper, we describe the process of VLSI circuit design, discuss abstraction of information processed by the circuit, and address the outline of system level test generation and fault simulation
Keywords :
VLSI; integrated circuit design; integrated circuit testing; VLSI circuit design; fault simulation; system level test generation; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Libraries; Logic; Registers; System testing; Very large scale integration;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562836
