• DocumentCode
    2957176
  • Title

    ASIC design considerations for address vector generation in memory test system

  • Author

    Ming, Han Wei ; Chun, Shi Wan

  • Author_Institution
    Inst. of Comput. Technol., Acad. Sinica, Beijing, China
  • fYear
    1996
  • fDate
    21-24 Oct 1996
  • Firstpage
    409
  • Lastpage
    412
  • Abstract
    In this paper an application-specific integrated circuit (ASIC) is presented for the generation of address vector of memory test system
  • Keywords
    application specific integrated circuits; integrated circuit design; integrated circuit testing; integrated memory circuits; random-access storage; VLSI RAM; address vector generation; application-specific integrated circuit; design; memory test system; Application specific integrated circuits; Circuit testing; Fault detection; Integrated circuit testing; Interference; Random access memory; Read-write memory; Semiconductor device testing; System testing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 1996., 2nd International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    7-5439-0940-5
  • Type

    conf

  • DOI
    10.1109/ICASIC.1996.562839
  • Filename
    562839
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2957176