Title :
A model of CMOS gate delay and projection of future trend
Author :
Chen, Kai ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
This paper reports a model for CMOS inverter propagation delay developed through SPICE simulation and some measurement. Together with the new mobility and the corresponding saturation current device models, projections of future CMOS gate performance within the environment of device scaling and supply voltage shrinking are presented
Keywords :
CMOS logic circuits; SPICE; carrier mobility; circuit analysis computing; delays; integrated circuit measurement; integrated circuit modelling; logic gates; technological forecasting; CMOS gate performance; CMOS inverter propagation delay; SPICE simulation; device scaling; future trend projection; low power supply voltage; mobility degradation; mobility model; saturation current device models; supply voltage shrinking; velocity saturation; CMOS technology; Capacitance; Equations; Inverters; MOSFET circuits; Predictive models; Propagation delay; SPICE; Semiconductor device modeling; Voltage;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562846
