A new contact programming ROM architecture for digital signal processor

Author

Takahashi, H. ; Muramatsu, S. ; Itoigawa, M.

Author_Institution

LEAD Design Group, Texas Instrum. Japan Ltd., Tokyo, Japan

fYear

1998

fDate

11-13 June 1998

Firstpage

158

Lastpage

161

Abstract

A new VIA-2 contact programming ROM architecture for quad level metal (QLM) process was developed, fabricated and tested with 100 MIPS 16 bit fixed point digital signal processor (DSP). The new ROM cell achieved nearly the same density as conventional diffusion programming ROM (only 4% bigger in area), high speed (106 MHz@VDD=1.66 V, 149 MHz@VDD=2.13 V), shorter (1/5) Turn Around Time (TAT), more immunity to process deviations, and confirmed 100 MIPS, 100 MHz operation with DSP (4.5 M Transistors) using 0.35 /spl mu/m 2.5 V/3.3 V dual gates CMOS QLM process technology.

Keywords

CMOS digital integrated circuits; digital signal processing chips; fixed point arithmetic; high-speed integrated circuits; read-only storage; 0.35 micron; 1.66 to 2.13 V; 100 MIPS; 106 to 149 MHz; 16 bit; 2.5 V; 3.3 V; Turn Around Time; VIA-2; contact programming ROM architecture; digital signal processor; dual gates CMOS QLM process technology; fixed point architecture; high speed ICs; process deviations; quad level metal process; CMOS technology; Circuits; Decoding; Digital signal processing; Digital signal processing chips; Digital signal processors; Logic; Parasitic capacitance; Read only memory; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688044

Filename

688044