DocumentCode
2957410
Title
FPGA Accelerated Computing Platform for MATLAB and C/C++
Author
Rasul, Rizwan ; Mutaal, Abdul ; Saqib, Nazar A. ; Kaleem, Mohammed ; Shaukat, Arslan ; Khanum, Aasia ; Khan, Muhammad Asad
Author_Institution
Dept. of Comput. Eng., Nat. Univ. of Sci. & Technol., Islamabad, Pakistan
fYear
2013
fDate
16-18 Dec. 2013
Firstpage
166
Lastpage
171
Abstract
With latest advancements in architecture, reprogram ability and availability of abundant on-chip resources, FPGAs (Field Programmable Gate Array) are used as hardware accelerators to speedup computationally intensive tasks with inherent parallelism. However non-availability of standard MATLAB and C/C++ computation routines and communication interface for general purpose programming restricted researchers and developers from easily utilizing the parallel computational ability of FPGAs in MATLAB and C/C++. In this article we propose a proof of concept implementation for software-hardware co-design that can be used with MATLAB and C/C++ to share the burden of intensified computing with the FPGA. Typical applications which can be divided into multiple tasks to be executed in parallel can be easily transferred to FPGA by utilizing the proposed method. Some of the applications which can efficiently use this concept are image processing, video processing, data encryption and data compression. Results obtained by using our method and routines implemented in software and hardware provide 50% to 100% computational acceleration, as compared to routines running in software on MATLAB running on a computer. The design and concept can aid developers to use FPGAs in combination with higher level computational languages such as MATLAB and C/C++.
Keywords
C++ language; cryptography; data compression; field programmable gate arrays; hardware-software codesign; mathematics computing; parallel processing; video signal processing; C language; C++ language; FPGA accelerated computing platform; MATLAB; architecture; communication interface; computational language; computationally intensive task; data compression; data encryption; field programmable gate array; general purpose programming; hardware accelerators; image processing; inherent parallelism; on-chip resources; parallel computational ability; parallel execution; reprogram ability; software-hardware codesign; video processing; Acceleration; Computer architecture; Field programmable gate arrays; Hardware; Libraries; MATLAB; C/C++; FPGA; GPU; Hardware Acceleration; MATLAB; MEX;
fLanguage
English
Publisher
ieee
Conference_Titel
Frontiers of Information Technology (FIT), 2013 11th International Conference on
Conference_Location
Islamabad
Print_ISBN
978-1-4799-2293-2
Type
conf
DOI
10.1109/FIT.2013.38
Filename
6717247
Link To Document