Title :
Advanced characterization method for sub-micron DRAM cell transistors
Author_Institution :
Oki Electr. Ind. Co. Ltd., Tokyo, Japan
Abstract :
An advanced characterization method for sub-micron DRAM cell transistors has been proposed for analysis of transistor test structures with actual memory cell patterns. In this method, new transistor parameters, Vgoff and Vgsat, have been considered for transistors´ off-leakage and full writing to storage node, respectively. These parameters are found to be good monitoring parameters for DRAM failures such as bit failures
Keywords :
CMOS memory circuits; DRAM chips; MOSFET; failure analysis; integrated circuit reliability; integrated circuit testing; leakage currents; CMOS DRAM process; DRAM bit failures; DRAM cell transistors; DRAM failures; characterization method; memory cell patterns; monitoring parameters; transistor off-leakage; transistor parameters; transistor storage node writing; transistor test structures; Capacitance; Capacitors; Contact resistance; Electrical resistance measurement; Low voltage; Pattern analysis; Random access memory; Testing; Transistors; Writing;
Conference_Titel :
Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on
Conference_Location :
Kanazawa
Print_ISBN :
0-7803-4348-4
DOI :
10.1109/ICMTS.1998.688048
