Comparison of Transconductance Reduction Techniques for the Design of a Very Large Time-Constant CMOS Integrator

This paper compares three transconductance (g_m) reduction techniques in terms of analog mismatch and total achievable amount of g_m reduction. The techniques investigated are current division, current cancellation, and cascade of gm-1/gm stages. Each of these is applied to the design of a very long time-constant integrator for use in a neural recording bladder control implant. Extensive Monte-Carlo simulations in a 0.35mum CMOS process showed that for the target gm of about 50 pA/V, the current division technique is the best option as it is insensitive to analog mismatch when used in closed-loop configuration. The achievable g_m with the current cancellation technique is limited to about 65 nA/V, whereas the cascade of gm-1/gm stages is extremely sensitive to DC offsets.