A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor

In an attempt to improve the speed of VLSI signal processing systems, a new architecture for a high-speed Multiply-Accumulate (MAC) unit optimized for digital filters is proposed. This unit is designed as a coprocessor for the LEON2 RISC processor. In this work, four parallel MAC units with two dual-port coefficient register files and a three-port general register file and a control unit are included in the coprocessing block. With the existence of four parallel units, several SIMD format instructions have been added to LEON2 instruction set. Each MAC unit has two 16-bit inputs, 32-bit output register and a programmable Round-Saturate block The MAC unit uses a new architecture which embeds the accumulate module within the partial products summation tree of the multiplier with minimum overhead. Our experimental results demonstrate a high performance in implementation of digital filters at elevated speeds of up to 33 millions of input samples per second in a 0.18 um technology.