Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers

Pipelined ADCs with open-loop residue amplifiers are currently gaining designers´ attention due to the simplicity of their design, their low-power and/or high-speed capabilities and their improved deep-submicron compatibility. Although several studies on power optimization of pipelined ADCs with closed-loop amplifiers are reported in literature, none so far addresses the power optimization problem of an open-loop implementation. Therefore, we propose a model for the open-loop pipelined ADC, based on which we perform calculations, resulting in optimum choices for design quantities, such as the number of bits per-stage and the sampling capacitors´ rate of scaling along the pipelined chain. Finally, we report on how these choices depend on the total ADC resolution and the technology in which the ADC is implemented.