A double level metallization system having 2 mu m pitch for both levels

Author

Doan, T. ; Bellersen, M. ; de Bruin, L. ; Godon, H. ; Grief, M. ; de Werdt, R.

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

1988

fDate

13-14 June 1988

Firstpage

13

Lastpage

20

Abstract

A double-layer metal (DLM) process having 2- mu m pitch for both metal levels has been successfully developed. This DLM system has been used in a 0.7- mu m CMOS process to fabricate 1-M SRAM and 256 K SRAM devices. Some relevant design rules are 1- mu m metal line and space for both levels, and 0.9- mu m contact and via openings. To meet these requirements, the process features planarization to minimize topology at LOCOS, polysilicon, and metal levels. The technological results are presented as well as reliability and electrical results. Photographs of fully processed and functional 256 K and 1-M high-performance SRAMs are shown.<>

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; metallisation; random-access storage; 0.7 micron; 2 micron; CMOS process; SRAM; contact openings; design rules; double level metallization system; electrical results; metal levels; pitch; planarization; reliability; via openings; CMOS technology; Electromigration; Laboratories; Manufacturing; Metallization; Planarization; Plugs; Random access memory; Space technology; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE

Conference_Location

Santa Clara, CA, USA

Type

conf

DOI

10.1109/VMIC.1988.14171

Filename

14171