An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture

This paper presents an experimental analysis of ReCoM, a novel reconfigurable architecture based on a mixed-grain reconfigurable array that combines a RISC microprocessor and a dynamically-configurable hardware for computation-intensive applications. The reconfigurable hardware is composed by mixed-grain reconfigurable cells that include 64-bits ALU, Look-Up Tables (LUTs), word-level arithmetic units and an efficient configuration and data memory architecture. To study the effectiveness of ReCoM on a well-known reference application, we implemented several FIR filters. The experimental results gathered through an accurate simulation model of ReCoM show performance figures encouragingly better than other DSP or alternative reconfigurable systems. Moreover, they demonstrate that ReCoM is very scalable and it successfully extracts the parallelism from streamed applications.