Power Modeling and Efficient FPGA Implementation of Color Space Conversion

In this paper we present a design for an efficient FPGA implementation of a color space converter in video compression. The proposed architecture is based on distributed arithmetic principles has been implemented on the Xilinx Virtex-2000E FPGA using a hybrid design approach combining Handel-C and VHDL. Maximum optimization of performance metrics including frequency and power has been achieved by careful manual floor planning of the design, with particular attention paid to the critical paths and pin assignment. Additionally, a novel functional level power analysis and modeling using non-linear regression analysis has been developed using power and energy data obtained for different combinations of system parameters.