A Novel CMOS Mini-LVDS Receiver for Flat-Plane Application

Author

Chen, Chung-Yuan ; Sun, Tai-Ping

Author_Institution

Nat. Chi Nan Univ., Hsien

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

260

Lastpage

263

Abstract

This paper presents the design for high speed flat-plane receiver circuit application. Due to the differential transmission technique and the low voltage swing, mini-LVDS (low-voltage differential signaling) allows high transmission speeds and low power consumption at the same time. High transmission speed with the minimum common-mode and differential voltage at the input for mini-LVDS application was achieved in the proposed receiver. The circuit was designed in a 3.3-V 0.35-mum CMOS technology, and the transmission operations is more than 500 Mb/s with random data patterns. The total power consumption is 3.5 mW.

Keywords

CMOS integrated circuits; integrated circuit design; low-power electronics; receivers; CMOS technology; differential transmission technique; differential voltage; flat-plane receiver circuit; high transmission speed; low power consumption; low voltage swing; low-voltage differential signaling; minimum common-mode voltage; novel CMOS miniLVDS receiver; power 3.5 mW; random data patterns; size 0.35 mum; voltage 3.3 V; CMOS technology; Circuits; Clocks; Costs; Electrical capacitance tomography; Energy consumption; Frequency; Hysteresis; Intersymbol interference; Low voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0395-2

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379775

Filename

4263353