• DocumentCode
    2958599
  • Title

    Performance Portability with the Chapel Language

  • Author

    Sidelnik, Albert ; Maleki, Saeed ; Chamberlain, Bradford L. ; Garzaran, Mara J. ; Padua, David

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
  • fYear
    2012
  • fDate
    21-25 May 2012
  • Firstpage
    582
  • Lastpage
    594
  • Abstract
    It has been widely shown that high-throughput computing architectures such as GPUs offer large performance gains compared with their traditional low-latency counterparts for many applications. The downside to these architectures is that the current programming models present numerous challenges to the programmer: lower-level languages, loss of portability across different architectures, explicit data movement, and challenges in performance optimization. This paper presents novel methods and compiler transformations that increase programmer productivity by enabling users of the language Chapel to provide a single code implementation that the compiler can then use to target not only conventional multiprocessors, but also high-throughput and hybrid machines. Rather than resorting to different parallel libraries or annotations for a given parallel platform, this work leverages a language that has been designed from first principles to address the challenge of programming for parallelism and locality. This also has the advantage of providing portability across different parallel architectures. Finally, this work presents experimental results from the Parboil benchmark suite which demonstrate that codes written in Chapel achieve performance comparable to the original versions implemented in CUDA on both GPUs and multicore platforms.
  • Keywords
    parallel architectures; parallel programming; parallelising compilers; software libraries; software performance evaluation; software portability; Chapel Language; Parboil benchmark suite; compiler transformation; explicit data movement; high-throughput computing architectures; hybrid machines; lower-level languages; parallel architectures; parallel libraries; parallel platform; performance optimization; performance portability; programming models; single code implementation; Arrays; Benchmark testing; Graphics processing unit; Multicore processing; Parallel processing; Reactive power;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International
  • Conference_Location
    Shanghai
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-4673-0975-2
  • Type

    conf

  • DOI
    10.1109/IPDPS.2012.60
  • Filename
    6267860