VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning

An analog neural network VHDL-AMS model is developed to analyze the performances of an IC architecture associated with a learning algorithm. We compare here an electrical simulation of a current mode architecture dedicated to deep submicronics technologies with a formal MATLAB^™ model. This comparison allows researching suitability between architecture and algorithm to optimize the learning speed versus the classification precision. It allows also to study the robustness of architecture versus electrical noise, component dispersions or memory loss and the robustness of an algorithm versus noise in the data´s.