• DocumentCode
    2959094
  • Title

    Tamper Resistivity Analysis for Nano-meter LSI with Process Variations

  • Author

    Ikeda, Makoto ; Yamauchi, Hiroshi ; Asada, Kunihiro

  • Author_Institution
    Univ. of Tokyo, Tokyo
  • fYear
    2006
  • fDate
    10-13 Dec. 2006
  • Firstpage
    387
  • Lastpage
    390
  • Abstract
    We have studied tamper resistivity with process variations. We have established a simulation platform to evaluate target LSI with differential electro-magnetic analysis. We have shown that wave dynamic differential logic (WDDL) becomes weak in terms of process variation. Based on the simulation platform, we have demonstrated several design styles including short wire, wire segmentation, and 3-wire, 3-phase systems.
  • Keywords
    cryptography; large scale integration; differential electromagnetic analysis; nanometer LSI; process variations; short wire; tamper resistivity analysis; three-phase systems; wave dynamic differential logic; wire segmentation; Analytical models; Antenna measurements; Conductivity; Cryptography; Large scale integration; Logic; Pattern analysis; Very large scale integration; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
  • Conference_Location
    Nice
  • Print_ISBN
    1-4244-0395-2
  • Electronic_ISBN
    1-4244-0395-2
  • Type

    conf

  • DOI
    10.1109/ICECS.2006.379806
  • Filename
    4263384
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2959094