Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits

The 3D Circuit technologies appear as a possible solution for interconnect optimization. For most of the 3D technologies, the 3D-Vias represent a very complex issue because of large pitch requirements and heavy usage of routing constraints. New algorithms and CAD methods must be developed in order to take advantage of the high integration of elements and potentially shorter wire lengths while keeping track of the 3D-Vias. One of the CAD problems, addressed by this paper, is the partition and placement of the I/O pins of a block into sub-blocks that are partitioned into the circuit tiers. In this paper, we extend our previous work in the field to trade-off the I/O pins balance for improved cut. The new version of our partitioning algorithm outperformed the widely used hMetis algorithm in number of 3D-Vias from 2% to 10% (depending on the I/O pins balance), while the standard deviation of the number of I/Os increased. We also observed that the maximum number of 3D-Vias between pairs of adjacent tiers dropped by 14% (in the best case) with the I/O pin unbalance.