DocumentCode
2959140
Title
Validation of RTL laser fault injection model with respect to layout information
Author
Papadimitriou, Athanasios ; Tampas, Marios ; Hely, David ; Beroulle, Vincent ; Maistri, Paolo ; Leveugle, Regis
Author_Institution
LCIS, Univ. Grenoble Alpes, Valence, France
fYear
2015
fDate
5-7 May 2015
Firstpage
78
Lastpage
81
Abstract
In order for modern security implementations to be trusted, they need to be successfully evaluated against hardware fault attacks. Lasers are excellent means of introducing either single or multiple, yet very precise, faults into an IC. Modeling of laser attacks at RTL can significantly help in securing a design during early design stages. An RTL fault model based on functional relations analysis, to extract localization information early in the design flow, has been proposed in previous works. In order to validate the accuracy of such a model, this paper compares predictions with post-layout results. First the RTL laser fault model is applied on several designs. Then results are compared with the fault space derived from layout, showing that the RTL predictions cover a large percentage of localized attacks.
Keywords
cryptography; integrated circuit layout; integrated circuit modelling; laser beam effects; RTL fault model; RTL laser fault injection model; functional relations analysis; hardware fault attack; integrated circuit faults; laser attacks; layout information; register transfer level; Circuit faults; Hardware; Integrated circuit modeling; Laser modes; Layout; Logic gates; Semiconductor lasers; Integrated circuits; Layout validation; RTL fault model; Security;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware Oriented Security and Trust (HOST), 2015 IEEE International Symposium on
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/HST.2015.7140241
Filename
7140241
Link To Document