DocumentCode
2959183
Title
An Ultra Low Power Successive Approximation ADC with Selectable Resolution in 0.13 μm CMOS Technology
Author
Arbat, A. ; Dieguez, Angel ; Samitier, Josep
Author_Institution
Univ. de Barcelona, Barcelona
fYear
2006
fDate
10-13 Dec. 2006
Firstpage
415
Lastpage
418
Abstract
A low power successive approximation analog-to-digital converter is presented operating at 1.2 V supply. The circuit has been designed in a 0.13 μm standard CMOS technology. The power consumption while converting is 13 μW, and in standby mode the power is reduced to 5.8 μW. The resolution is programmable between 1 to 8 bits. It can work from 500 Hz up to 50 kHz clock frequencies.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; ADC; analog-to-digital converter; frequency 500 Hz to 50 kHz; power 13 μW; power 5.8 μW; size 0.13 μm; standard CMOS technology; standby power mode; ultra low power successive approximation; voltage 1.2 V; Analog-digital conversion; CMOS technology; Capacitors; Circuits; Digital-analog conversion; Energy consumption; Frequency conversion; Microprocessors; Sampling methods; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on
Conference_Location
Nice
Print_ISBN
1-4244-0394-4
Electronic_ISBN
1-4244-0395-2
Type
conf
DOI
10.1109/ICECS.2006.379813
Filename
4263391
Link To Document