Reliable and low cost wafer level packaging. Process description and qualification testing results for wide area vertical expansion (WAVE TM) package technology

A number of companies around the world are developing or have begun offering devices processed and packaged in the wafer format. Most of these competing concepts involve the creation of a redistribution layer over the face of the chip, a method long employed by IBM in the development of its well known flip-chip C4 processes. Wafer level packaging has the potential for transforming IC packaging from a labor intensive process of making wire bonds one-at-a-time on individual die, to a batch process, much like wafer fabrication. Tessera has developed a unique approach to wafer level packaging that provides a physically robust, compliant structure while offering significant cost reduction through a unique method of mass termination and encapsulation. In this paper, the authors describe the materials and process developed for utilization of “wide area vertical expansion” (WAVE^TM ), producing what may prove to be the most reliable chip-size package available. To back up this rather bold statement, the environmental test program description is outlined and test data is offered for review