Title :
Stacked Half-Milli CSP
Author :
Chino, Mitsuru ; Tsuchihashi, Ken-ichi ; Miyajima, Kenji
Author_Institution :
Misuzu Ind. Corp., Nagano, Japan
Abstract :
A new thin (0.5 mm thick) package named “Half-Milli CSP” was developed. Conventional assembly processes such as die attach, wire bonding, and encapsulation with the screen printing method were used and improved to apply this package. This structure is a cavity down BGA with a PCB substrate. The package substrate is engraved and the die is put into this device-hole. This method makes the package thinner than conventional FBGAs. Furthermore, a double-sided wiring substrate is used for the Half-Milli CSP. Therefore, package level stacking can be easily achieved by installing the electrodes in both sides of the substrate. This package is mounted on PCBs with current technology and reflow soldering. Also, it has the same performance as conventional FBGA in terms of reliability, cost and SMT
Keywords :
ball grid arrays; chip scale packaging; electrodes; encapsulation; integrated circuit interconnections; integrated circuit reliability; lead bonding; reflow soldering; surface mount technology; 0.5 mm; FBGAs; Half-Milli CSP; PCB substrate; SMT; assembly processes; cavity down BGA; device-hole; die attach; die placement; double-sided wiring substrate; electrodes; encapsulation; engraved package substrate; package cost; package level stacking; package mounting; reflow soldering; reliability; screen printing method; stacked Half-Milli CSP; thin package; wire bonding; Assembly; Bonding; Chip scale packaging; Electrodes; Encapsulation; Microassembly; Printing; Stacking; Wire; Wiring;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-6482-1
DOI :
10.1109/IEMT.2000.910722
