Jitter model of direct digital synthesis clock generators

Direct Digital Synthesis (DDS) has become a popular technique for synthesis of very accurate clocks. For example, in Digital Television (DTV) an audio data stream must be inserted into a video data stream, which implies that we must synchronize the audio clock with the video clock. According to the digital audio standard, the audio clock frequency is 5,6448 MHz and with PAL digital television standard, the video clock frequency is 35.46895 MHz. In this case, the division ratio is 112896/709379. Other division ratios are required with other DTV standards such as NTSC, SECAM or HDTV, and with other digital audio standard frequencies. This paper outlines a jitter model applicable to direct digital synthesis (DDS) clock generators. It is based on a Fourier analysis of the output signal when the DDS is corrupted by the most common error sources. This model is applicable to the design of DDS subject to stringent jitter constraints