Title :
Low-thermal-resistance flip-chip fine package for 1-W voltage regulator IC
Author :
Takamura, Fumio ; Tanaka, Kenji ; Mitsuka, Kaoru ; Matsushita, Hikari
Author_Institution :
Semicond. Technol. Headquarters, New Japan Radio Co. Ltd., Saitama, Japan
Abstract :
A low-thermal-resistance flip-chip fine package (FFP) for a voltage regulator IC is described. This FFP is a chip size package (CSP) developed for low-pin-count ICs. It consists of an alumina ceramic substrate, flip-chip bonded ICs and underfill resin. The thermal conductivity of the alumina ceramic substrate is about 50 times greater than that of the resin used in conventional plastic mold packages. The thermal path from the heat source in the IC chip to the substrate is very short because the IC, which has Au bumps, is flip-chip bonded to the metal pattern on the ceramic substrate. This offers superior thermal resistance to that in conventional plastic mold packages. The finite element method (FEM) was used to simulate the thermal resistance reduction effects of varying the substrate size and material, the copper-pattern area and the via holes on the printed circuit board (PCB). An actual thermal resistance of 130°C/W (0.96 W power dissipation at Tj=150°C) was observed in a 3.0×3.0×0.65 mm FFP mounted on a 6×10 mm copper-pattern PCB. This value is almost the same as that arrived at in simulations, and that of To-252, a conventional plastic mold package
Keywords :
ceramic packaging; chip scale packaging; circuit simulation; encapsulation; finite element analysis; flip-chip devices; integrated circuit interconnections; integrated circuit measurement; microassembling; power integrated circuits; thermal conductivity; thermal resistance; voltage regulators; 0.65 mm; 0.96 W; 1 W; 10 mm; 150 C; 3 mm; 6 mm; Al2O3; Au; Au bumps; CSP; Cu; FEM; PCB; alumina ceramic substrate; ceramic substrate; chip size package; copper-pattern PCB; copper-pattern area; finite element method; flip-chip bonded ICs; flip-chip bonding; flip-chip fine package; heat source; low-pin-count ICs; metal pattern; plastic mold packages; power dissipation; printed circuit board; simulation; substrate material; substrate size; thermal conductivity; thermal path; thermal resistance; thermal resistance reduction effects; underfill resin; via holes; voltage regulator IC; Bonding; Ceramics; Circuit simulation; Integrated circuit packaging; Plastic packaging; Regulators; Resins; Thermal conductivity; Thermal resistance; Voltage;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-7803-6482-1
DOI :
10.1109/IEMT.2000.910742