A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD. Fine locking is achieved by the phase shifter for the sake of fast locking. Measure results show that the maximum clock skew of the proposed SMD is 33.64 ps in the frequency range from 200 to 450 MHz and that the consumption power is 9.71 mW at 450 MHz in a 0.18-mum 1P6M N-well CMOS process at 1.8 V power supply. The total locking time is less than 10 clock cycles.