Simulating the Effects of Process Variations on Capacitive Crosstalk

Process variations have an enormous impact on the amount of crosstalk in the circuit. Aggravation in crosstalk may lead to erroneous behavior of the circuit resulting in reduced product yield. Products have failed to meet targeted frequencies because of crosstalk problems. Therefore, a circuit should be designed such that there is a safety margin from erroneous circuit operation. At the same time, the design should not be so conservative that chip area and performance fall behind operational objectives. Whereas the combination of process parameters that give rise to worst-case noise is context dependent, we show in this paper how to efficiently determine process corners that can be used to approximate the worst-case crosstalk pulse or delay at the crosstalk site. Our experimental results show the accuracy gain of our process corners compared to traditional techniques while maintaining efficiency.