Parallel digital architectures for high-speed adaptive DSSS receivers

DSP-based implementations of receivers have many advantages over their analog counterparts including precise matched filtering and reconfigurability. As processing rates increase, more receiver functions are implemented digitally-the ultimate goal in this shift being all-digital receivers which sample at IF or RF. Practical limitations obviously occur when the processing rates fall behind sampling and symbol rates. We extend previous ideas for introducing parallelism into the receiver design. We describe a parallel, adaptive DSSS receiver in which individual processing units can potentially operate at rates below the symbol rate. The design is shown to have BERs equivalent to conventional designs.