Power implications of precision limited arithmetic in floating point FIR filters

This work targets characterization of the architectural power implications of precision limited arithmetic operations during floating point FIR filtering. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. The experiments substantiate the validity of our transition activity scaling based approach for the design of low power floating point adders and multiply accumulators (MACs). With precision limited low pass filtering, the worst case power reduction offered by the proposed transition activity scaled triple data path floating point adder (TDPFADD) is better than 60%. The corresponding reduction in power delay product is better than 75%