Architectural evaluation of flexible digital signal processing for wireless receivers

The combined requirements for high-performance, low-power and flexibility is the critical design issue for future wireless digital receivers. We propose using function-specific architectures to provide sufficient flexibility identified at system level that have low energy consumption overhead. In this paper, we evaluate this approach and compare energy efficiency and computation density to other reconfigurable architectures based on different configuration granularities. Two major processing blocks of an OFDM receiver, FFT and Viterbi decoder, are used as design examples.